In current CMOS technology, devices generally are made on one specific semiconductor substrate with a single crystal orientation. However, in silicon, electrons have their greatest mobility in the {100} family of planes, while holes have their greatest mobility in the {110} plane family. Generally, one or the other of a P-FET or an N-FET is implemented with the optimum crystal orientation, while the other functions with less than optimal carrier mobility because it is implemented with the same crystal orientation. U.S. Pat. No. 4,857,986 to Kinugawa, which is hereby incorporated herein by reference, describes some of the effects of crystal orientation on carrier mobility.
Accordingly, one problem with the prior art is that the mobility of both electrons and holes is not optimized. Because the mobility of one type of carrier is not optimized, devices may take up more real estate on a substrate in order to meet performance requirements. This larger device footprint generally increases the difficulty of designing system-on-a-chip implementations, which may require a large number of devices on a single chip.
Another problem in the prior art caused by using both P-FETs and N-FETs in a SOI substrate with single crystal orientation generally is potentially severe floating body effect, and the resulting history effect. Moreover, it may increase the difficulty in meeting ESD specifications.
Workers have recognized these problems and have developed techniques for fabricating CMOS devices on hybrid substrates with multiple crystal orientations. For example, U.S. Pat. No. 5,384,473 to Yoshikawa et al., which is hereby incorporated herein by reference, describes a method for fabricating P-FETs on (110) surfaces and N-FETs on (100) surfaces through wafer bonding and selective epitaxy. Yoshikawa et al.'s method is summarized in the following paragraphs and in FIG. 1.
FIGS. 1A to 1G are cross sectional views in the manufacturing sequence of a semiconductor device according to the prior art. First prepared are a single-crystal silicon substrate (wafer) 10 in which the (100) plane comes out to the main surface and a single-crystal silicon substrate (wafer) 12 in which the (110) plane appears at the main surface (FIG. 1A).
Then, as illustrated in FIG. 1B, the substrate 10 is laminated to the substrate 12 by, for example, planishing adhesion techniques to form a silicon body 20.
Next, in FIG. 1C, a mask material 14 is formed on the substrate 10. With the mask material 14 as a mask, the substrate 10 is etched to make an opening 18 that allows the main surface of the substrate 12 to appear at the bottom.
Then, as shown in FIG. 1D, a sidewall 50 made of, for example, a silicon nitride film is formed on the side of the opening 18. This sidewall 50 is created by forming, for example, a nitride film over the substrates 10 and 12, and etching the nitride film by RIE or anisotropic etching techniques to leave a nitride film in the form of a sidewall on the side of the opening 18.
Next, as illustrated in FIG. 1E, by using the mask material 14 as a mask, an epitaxial silicon layer 52 is grown on the substrate 12 exposed at the bottom of the opening 18. The epitaxial silicon layer 52 is formed by a selective epitaxial growth (hereinafter, referred to as SEG) method that uses the substrate 12 as seed crystal. This permits the plane whose surface orientation is the same as that of the main surface of the substrate 12, or the (110) plane to appear at the surface of the epitaxial silicon layer 52. Here, by controlling the thickness of the epitaxial silicon layer 52 to be grown, the surface of the epitaxial silicon layer 52 may be made almost flush with the surface of the substrate 10. Therefore, the silicon body 20 has portions of different surface orientations: a portion with the (100) plane and a portion with the (110) plane. Further, in the body 20 of FIG. 1E, those portions of different surface orientations may be made flush with each other. The mask material 14 is then removed from over the substrate 10.
Then, in FIG. 1F, with a photoresist (not shown) as a mask, p-type impurities are introduced into the substrate 10 with the (100) surface orientation. By using a new photoresist (not shown) as a mask, n-type impurities are then introduced into the epitaxial silicon layer 52 with the (110) surface orientation. Next, the introduced impurities are activated to form a p-type well 22 in the substrate 10, and an n-type well 24 in the epitaxial silicon layer.
Finally, as shown in FIG. 1G, an NMOS 26 is formed in the p-type well 22, and a PMOS 28 is formed in the n-type well 24. This completes the semiconductor device fabrication using hybrid substrates with multiple crystal orientations in accordance with the prior art.
A noted advantage of the hybrid structure shown in FIG. 1G is that it enables the portions of different surface orientations to be almost flush with each other. As a result, there is no step or gap between portions of different surface orientations. This facilitates the connection of semiconductor elements by the interconnection layer. It also eliminates depth of focus problems with lithography. In order to achieve this advantage, it is very important to precisely control the silicon epitaxy 52, FIG. 1E, so that the surface of the epitaxial silicon layer 52 is almost flush with the surface of the substrate 10.
One significant problem commonly encountered in achieving this is the so-called micro-loading effect. This effect stems from variations in transport phenomena across the surface of a patterned wafer. Using etching as an example, the micro-loading effect causes wide trenches to etch more rapidly than narrow trenches. It also causes the open end of a trench to etch more rapidly than the base of a trench. These variations in etch rate are caused by well-known differences in mass and heat fluxes created by the features of the patterned wafer.
The micro-loading effect is also a known problem in chemical mechanical polishing (CMP) used for planarization of wafers. Areas of the wafer that are locally sparse or dense create non-uniformity in the etching/polishing rate. This may cause unacceptable post polish film thickness variation including dishing. Dishing results from an area of lower pattern density polishing faster than an area with a higher pattern density, thus forming a dish-shaped surface.
The micro-loading problem also manifests itself when fabricating FETs on hybrid crystal orientations. In particular, micro-loading can occur during the silicon epitaxy process. This causes wide openings to grow slower than small openings. In order to avoid a step between regions of different crystal orientation, an additional planarization step is required, thereby adding cost and complexity to the process.
What is needed is a method for controlling the micro-loading effect without adding unnecessary complexity or cost.